The present invention relates to a mounting technology for integrated circuit (IC) chips (hereinafter “chips”) and, more specifically, to a chip mounting structure and manufacturing method for a chip mounting structure in which the pitch (interval) between bumps has been narrowed in a flip-chip connection.
Bumps, such as solder bumps, are used in a flip-chip connection between a semiconductor chip and the board supporting the chip. These bumps are arranged in an array on the connection surface of the chip at a pitch, for example, from 150 μm to 200 μm.
Japanese Patent Publication Number 08-111432 (Application Number 06-246469) discloses a semiconductor device in which the positions of wide pads are alternately shifted in the lead connections between a semiconductor chip and the resin package surrounding it and the leads are arranged on the resin package so that the pads do not establish contact between each other.
Japanese Patent Publication Number 2006-114741 (Application Number 2004-301385) discloses a multi-layer core board in which tapered via hole conductors extending into the multi-layer core board through a cladding layer in insulated spots to a power supply layer, and tapered via-hole conductors extending through the power supply layer in insulated spots to the cladding layer are arranged in alternating fashion so as to narrow the pitch between via holes.